Arithmetic must have, but, according to the 100 m timing constraints when I was a lot of warning


How to do arithmetic, guarantee the timing constraints can be, not a bunch of warning:

R_dac_data & lt;=r_dac_value [r_idx] * r_env_k/255;

A multiplication and division

CodePudding user response:

Unless you count the data bits wide, the FPGA is best not to use directly * and/with IP IP multiplication and division,

CodePudding user response:

reference 1/f, macro hadron response:

unless you count the data bits wide, the FPGA is best not to use directly, * and/with IP IP multiplication and division,

comprehensive device will call integrated into IP core

CodePudding user response:

refer to the second floor number007cool response:

Quote: refer to 1st floor macro hadron response:

unless you count the data bits wide, the FPGA is best not to use directly, * and/with IP IP multiplication and division,

comprehensive device will call integrated into IP core of

That you examine timing warning is what

CodePudding user response:

The denominator is constant, not when processing division, after comprehensive optimization generally optimized shift addition and subtraction, the multiplication of two variables optimization before but not to drop, comprehensive device is to be able to call the IP, but the result is bad, the clock can not too high, the ideal way is to call their IP or chip DSP unit, when the two variable width is not very big, can separate expression, use two clock to clap, first by again except the
For example:
R_dac_data_r1 & lt;=r_dac_value [r_idx] * r_env_k;
R_dac_data & lt;=r_dac_data_r1/255;
By the way, the constant division, comprehensive device will be optimized, similar to the C language compiler magic number optimization,
For example: x/255=256 + x/x/(256 * 256)=x & lt; <8 + x<16.//(approximately equal to)
This constant number immediately division, can be directly used in expression, delay of addition,