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Verilog language beginner

Time:12-03

I in the realization of a simple, small switch key control lights, I come in the modelsim simulation, this is my light_led file, and testbeach files, ask bosses, I this why the waveform,
Programming
The module light_led (key, led_out);
Input the key;
The output led_out;
Reg out;
Wire key;
Wire led_out;
Initial the begin
Out=1 'b0;
End
Always @ (key)
The begin
If (key)
Out=1 'b1;
Else if (! Key)
Out=1 'b0;
End
The assign led_out=out;
Endmodule
Tsatbeach coding
` timescale 1 ms/ms
The module light_led_tb ();
Reg key;
Reg out;
Wire led_out;
Initial the begin
# 5 key=1 'b1;
# 50 key=1 'b0;
End
Light_led (
The key (key),
Out (out),
. Led_out (led_out)
);
Endmodule
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