Presence of bosses will the FPGA design, realize data acquisition of DS18B20. Do have a bounty!!!!!!-CodePudding

As long as the program and the simulation can!!!! Thank you bosses, the bounty of discussion,
Qq: 1129220403, WeChat: q1129220403

Main requirements: 1, the realization of UART functions; 2, the data acquisition; 3, implement the data record and export; 4, implement display,
Platform: Quartus Ⅱ, language: verilog, shows the available LCD,

CodePudding user response:

You these functions, in each fpga development board has routines, see can solve,

CodePudding user response:

For small white has just started to learn, have time is ok, at least I personally have the self-confidence, but for now, the time is too tight, busy and a lot of things, so I want to find a big help, have a small design,