Home > other >  Refer [white] the same Verilog simulation test files, and sometimes through, and sometimes not, this
Refer [white] the same Verilog simulation test files, and sometimes through, and sometimes not, this

Time:12-05



But a few minutes ago is a waveform

CodePudding user response:

Software bug, restart software with respect to OK

CodePudding user response:

reference 1st floor AccFPGA response:
software bugs, restart the software with respect to OK
restart the software still couldn't get through,,, is it possible to be the installation of the software package

CodePudding user response:

Exit, find out a project folder where *. Sim folder, delete the folder, line, may be some file delete not to drop, ignore it,

CodePudding user response:

reference qq_708907433 reply: 3/f
exit, will project in the folder to find *. Sim folder, delete the folder, line, may be some file delete not to drop, ignore it,
deleted or I can't, and still the same
  • Related