Before entering a company internship, I just didn't contact with verilog language, today the teacher asked me to write the three modules, said let me take a look at spi, asynchronous FIFO, I feel like meng meng,
by theirThe spi in gourd painting gourd ladle written? The two module also don't know how to write?
Teacher said I could write a test document
I now head is full of question marks? Have a great god gives directions give me article refers to the way I then how to learn this knowledge? Before (my major is information engineering hardware only learned a fur electric VHDL)
Stick the spi that a piece of code
The module SPI
(
The input I_clk,//the clock signal
Input I_rst,//reset
Input I_rx_en,//allowed to read data
Input I_tx_en,//to allow data
Input [away] I_data_in,//
The output reg [away] O_data_out,//
The output reg O_tx_done,//transport complete logo
The output reg O_rx_done,//read complete sign
//spi signal definition
The output reg O_CS,//choose
The output reg O_SCLK,//the clock
The output reg O_SDI,//output
Input I_SDO//input
);
//state choose
0 to 15, speaking, reading and writingReg [3-0] R_tx_state;
Reg [3-0] R_rx_state;
Always @ (posedge I_clk or negedge I_rst)
The begin
if(! I_rst)//reset response
The begin
R_tx_state & lt; D0=4 ';
R_rx_state & lt; D0=4 ';
O_data_out & lt; D0=8 ';
O_tx_done & lt; D0=1 ';
O_rx_done & lt; D0=1 ';
O_SDI & lt; D0=1 ';
O_SCLK & lt; D0=1 ';
O_CS & lt; D1=1 ';
End
Else if (I_tx_en) signal//
The begin
O_CS & lt; D0=1 ';
Case (R_tx_state)
4 'd1, 4' d3, 4 'd5, 4' d7, 4 ', 4 'd9 d11, 4', 4 'd13 d15://integration of odd number
The begin
R_tx_state & lt;=R_tx_state + 1 'b1;
O_tx_done & lt;=1 'b0;
O_SCLK & lt;=1 'b1;
End
4 'd0://7
The begin
R_tx_state & lt;=R_tx_state + 1 'b1;
O_tx_done & lt;=1 'b0;
O_SDI & lt;=O_data_out [0];
O_SCLK & lt;=1 'b0;
End
4 'sixth in d2://
The begin
R_tx_state & lt;=R_tx_state + 1 'b1;
O_tx_done & lt;=1 'b0;
O_SDI & lt;=O_data_out [1];
O_SCLK & lt;=1 'b0;
End
4 'd4://fifth
The begin
R_tx_state & lt;=R_tx_state + 1 'b1;
O_tx_done & lt;=1 'b0;
O_SDI & lt;=O_data_out [2];
O_SCLK & lt;=1 'b0;
End
4 'fourth d6://
The begin
R_tx_state & lt;=R_tx_state + 1 'b1;
O_tx_done & lt;=1 'b0;
O_SDI & lt;=O_data_out [3].
O_SCLK & lt;=1 'b0;
End
4 'd8://third
The begin
R_tx_state & lt;=R_tx_state + 1 'b1;
O_tx_done & lt;=1 'b0;
O_SDI & lt;=O_data_out [4];
O_SCLK & lt;=1 'b0;
End
4 'second d10://
The begin
R_tx_state & lt;=R_tx_state + 1 'b1;
O_tx_done & lt;=1 'b0;
O_SDI & lt;=O_data_out [5];
O_SCLK & lt;=1 'b0;
End
4 'd12://the first
The begin
R_tx_state & lt;=R_tx_state + 1 'b1;
O_tx_done & lt;=1 'b0;
O_SDI & lt;=O_data_out [6].
O_SCLK & lt;=1 'b0;
End
4 'd14://zero
The begin
R_tx_state & lt;=R_tx_state + 1 'b1;
O_tx_done & lt;=1 'b1;
O_SDI & lt;=O_data_out [7];
O_SCLK & lt;=1 'b0;
End
Default: R_tx_state & lt; D0=4 ';
Endcase
End
Else if (I_rx_en)//collect signal
The begin
O_CS & lt;=1 'b0;//lower slice signal CS
Case (R_rx_state)
4 'd0, 4' d2, 4 'd4, 4' d6, 4 'd8, 4' d10, 4 'd12, 4' d14://integration even state
The begin
O_SCLK & lt;=1 'b0;
R_rx_state & lt;=R_rx_state + 1 'b1;
O_rx_done & lt;=1 'b0;
End
4 'd1://receive the 7th
The begin
O_SCLK & lt;=1 'b1;
R_rx_state & lt;=R_rx_state + 1 'b1;
O_rx_done & lt;=1 'b0;
O_data_out [7] <=I_SDO;
End
4 'd3://receiving sixth
The begin
O_SCLK & lt;=1 'b1;
R_rx_state & lt;=R_rx_state + 1 'b1;
O_rx_done & lt;=1 'b0;
O_data_out [6] <=I_SDO;
End
4 'd5://receive 5
The begin
O_SCLK & lt;=1 'b1;
R_rx_state & lt;=R_rx_state + 1 'b1;
O_rx_done & lt;=1 'b0;
O_data_out [5] <=I_SDO;
End
4 'd7://receiving 4
The begin
O_SCLK & lt;=1 'b1;
R_rx_state & lt;=R_rx_state + 1 'b1;
O_rx_done & lt;=1 'b0;
O_data_out [4] <=I_SDO;
End
4 'd9://receiving third
The begin
O_SCLK & lt; nullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnull
