Introduced the following a few simple Verilog HDL, and then we analyzed Verilog HDL program features,
Case (3.1.1) : the module adder (count, sum, a, b, cin);
Input (2-0) a, b;
Input cin.
The output count;
The output [2-0] sum;
The assign {count, sum}=a + b + cin;
Endmodule
This example through continuous assignment statement describes a called adder three adder can according to the number two and three bits a, b, and carry (cin) and calculated (sum) and carry (count), can be seen from the example of the Verilog HDL program is nested in the module and endmodule statements,
Case [3.1.2] : the module compare (equal, a, b);
The output equal;//statement output signal equal
Input (1-0) a, b;//declare the input signal. A, b
The assign equal=(a==b)? 1-0.
/* if a, b two input signals are equal, the output is 1, otherwise 0 */
Endmodule
This program through continuous assignment statement describes a comparator, called the compare of the two bits a, b, such as a and b are equal, the output is equal to high level, otherwise as low level, in this program,/*... */and//... Said the comments section, annotation is just for easier for programmers to understand program, is ineffective to compile,
Case [3.1.3] : the module trist2 (out, in, enable);
The output out;
Input in the enable;
Bufif1 mybuf (out, in, enable);
Endmodule
This application describes a called trist2 tristate driver, program by calling a existing in the Verilog language library bufif1 tristate driver instance element to realize its function,
Case [3.1.4] : the module trist1 (out, in, enable);
The output out;
Input in the enable;
Mytri tri_inst (out, in, enable);
//call the mytri module defines an instance of the element tri_inst
Endmodule
The module mytri (out, in, enable);
The output out;
Input in the enable;
Assign out=enable? In: 'bz.
Endmodule
This example program by another method describes a tri-state gate, in this case there are two modules, module trist1 call tri_inst instance component, defined by the module mytri module trist1 is the top-level module, the module mytri is called child module,
Through the example above you can see:
? Verilog HDL program is composed of modules, each module is embedded in the content of the module and endmodule two
Between statements, each module to achieve a specific function, the module can be nested hierarchy, and because of that, just can
To large digital circuit design divided into different small module to achieve a specific function, at last, through the top-level module
Call module to achieve the overall function,
? Each module should undertake port definitions, indicating the I/o port, and then on the function of the module behavior logic description,
? Verilog HDL programs written form freedom, a line can write a few statements, a statement can write more lines,
? Besides endmodule statements, each statement and the end of the data definition must have a semicolon,
? You can use the/*... */and//... For any part of the Verilog HDL program comments, a good, have the
With the value of the source program should be combined with the necessary comments, in order to enhance the readability and maintainability of the program,