I am using spi transmission between fpga and AD, AD data collected is 18, the spi transmission data must be in his 8 bits of a frame or in the 16 bits of a frame? Can a frame for 18?

CodePudding user response:

Carefully read the AD manuals, the transmission must be according to the AD of the SPI manual, can find the answer in the manual,

CodePudding user response:

Data: 8 bit/16 bit/24 bit

CodePudding user response:

Can, SPI essence is a loop synchronous shift register, as long as the sender and the receiver have a common agreement, can

CodePudding user response:

reference 1st floor qq_708907433 response:

AD manuals carefully read, the transfer must be according to the AD of the SPI manual, can find the answer in the manual,

+ 1

CodePudding user response:

AD chip must be SPI in the manual transmission requirements, timing, data bits, bit sequence will have instructions, I estimate that the FPGA as the main equipment, in accordance with the requirements for AD chip manual output SPI clock to the AD, in the AD internal register address written on the MOSI cable configured, configuration and then through the MISO address data within the data line read AD the converted data is read, CE or CS, of course, this process can make the signal is in a valid state, important is written according to the AD manual timing,