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VHDL simulation waveforms when a signal into a high impedance state, why?

Time：12-06

Is written in the quartus ii the VHDL language, the simulation waveform, the lowest one signal into a high impedance state, what reason be? How to solve?

CodePudding user response:

Great may be logical didn't use to be optimized in out

CodePudding user response:

The simulation timing are unreasonable design

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