The FPGA on verilog module in the call-CodePudding

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The FPGA on verilog module in the call

Time：12-13

In the sealing layer calls multiple module, the module of some of them have the same output, how to solve the problem of multiple replication, can selectively call different module, I use the terms of a flag=0 and!=0, write this condition at the bottom of the module to avoid repeat the assignment, but seems to be instantiated or not,

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