Third, check the information, it is said that the CPU will complete finish that has * * * * * * * * MEM stage instruction, then the exception victim positioning in a (following) instruction, then asked how to answer 2, 3,

Regarding the questions, I query information, I think two small q, ALU overflow has high priority, is right?

Thank you


3. A processor is executing code and executes A divide instruction that divides by zero.
(a) the Describe in the MIPS instruction set what the state needs to be saved by the hardware interrupt mechanism.
(b) Assume that the interrupt handler reads registers R5, R6 and R7 and writes registers R5, the R8 and R10. What registers does the interrupt handler need to save?
(c) What the state does the ERET instruction change?

4. An instruction takes the following synchronous exceptions: instruction Address Exception, ALU Overflow. What should the interrupt cause be the loaded with? What if that same instruction has an external interrupt pending? Explain your reasoning?