Operating system version: Linux p2020rdb 4.19.68 ga5c3ba83f - dirty # 18 SMP PREEMPT Mon Mar 30 14:01:04 CST 2020 PPC GNU/Linux


Hardware card by powerpc p2020

Problem description: p2020 with fpga (K7) directly connected, p2020 doorbell, can receive K7, K7 doorbell, p2020 without interruption



The log in detail as follows:


1. The uboot
TLB flasjh esel=2
Flash: bank num=0
Bank num and size=8388608
Bank num and size=8388608
Bank num=1
Bank num and size=134217728
Bank num and size=67108864
Bank num=2
Bank num and size=134217728
Bank num and size=67108864
Bank num=3
Bank num and size=8388608
Bank num and size=8388608
Bank num=4
Bank num and size=8388608
Bank num and size=8388608
Flash size=159383552
152 MiB
L2:512 KiB enabled
SRIO1: enabled
SRIO2: enabled
MMC: FSL_SDHC: 0
PCIe1: disabled
PCIe2: disabled
In: serial
Out: serial
Err: serial
Net: phy interface=1
Phy interface else=1
ETSEC2 (PRIME)




2. The dmesg srio

[0.183895] FSL - of - Rio ffec0000. Rapidio: of - device full name/rapidio @ ffec0000
[0.189750] FSL - of - Rio ffec0000. Rapidio: Regs: [mem xffec0000 xffed0fff 0 0]
[0.195478] FSL - of - Rio ffec0000. Rapidio: bellirq: 57
[0.199076] FSL - of - Rio ffec0000. Rapidio: pwirq: 16
[0.202556] FSL - of - Rio ffec0000. Rapidio:/rapidio @ ffec0000/port1: LAW start 0 x0000000ca0000000, size 0 x0000000000010000.
[0.212088] FSL - of - Rio ffec0000. Rapidio: the Hardware port width: 4
[0.216687] FSL - of - Rio ffec0000. Rapidio: Training the connection status: Single - lane 0
[0.222931] FSL - of - Rio ffec0000. Rapidio: rapidio Common Transport System size: 256
[0.234826] FSL - of - Rio ffec0000. Rapidio:/rapidio @ ffec0000/port2: LAW start 0 x0000000cb0000000, size 0 x0000000000010000.
[0.244336] FSL - of - Rio ffec0000. Rapidio: the Hardware port width: 4
[0.248912] FSL - of - Rio ffec0000. Rapidio: Training the connection status: Single - lane 0
[0.255167] FSL - of - Rio ffec0000. Rapidio: rapidio Common Transport System size: 256
[0.613825] rio_mport: Added RIO mport 0 cdev (251-0)
[0.617566] rio_mport: Added RIO mport 1 cdev (251:1)
RIO: [1.217908] rio_register_scan for mport_id=1
[1.217964] rio_cm: riocm_init Registered class with 250 major
[1.217976] rio_cm: riocm_add_mport add mport RIO mport 0
[1.219318] rio_cm: riocm_add_mport add mport RIO mport 1
[1.220958] rio_cm: riocm_cdev_add Added rio_cm cdev (250-0)

3. The interrupt
CPU0 CPU1
16:16 Level 0 0 OpenPIC port - write
19:19 Level 0 0 OpenPIC FSL - LBC
24:0 2 OpenPIC 6 Level mdio @ ffe24520:05
35:53 OpenPIC 35 0 Level eth1_g0_tx
36:1012 0 OpenPIC 36 Level eth1_g0_rx
40:40 Level 0 0 OpenPIC eth1_g0_er
42:3211 0 42 Level OpenPIC ttyS0
47:0 0 OpenPIC 47 Level gpio - cascade
57:57 Level 0 0 OpenPIC dbell_rx
60 Level 60:0 0 OpenPIC msg_tx
61:0 0 OpenPIC 61 Level msg_rx
62:0 0 OpenPIC 62 Level msg_tx
63:0 0 OpenPIC 63 Level msg_rx
68:0 0 OpenPIC 68 Level ptp_qoriq
507:13083 13046 2043 Edge OpenPIC ipi call function
508:2500 3425 2044 Edge OpenPIC ipi reschedule
509:0 0 OpenPIC 2045 Edge ipi tick - broadcast
LOC: 7464, 3472 Local timer interrupts for the timer event device
BCT: 0 0 Broadcast the timer interrupts for the timer event device
LOC: 2 2 Local timer interrupts for others
The SPU: 0 0 Spurious interrupts
PMI: 0 0 Performance monitoring interrupts
MCE: 0 0 Machine check exceptions
NMI: 0 0 System Reset interrupts


4. The dmesg
[0.000000] barrier - nospec: patched 193 locations
[0.000000] Top of RAM: 0 x20000000, Total RAM: 0 x20000000
[0.000000] the Memory hole size: 0 MB
[0.000000] Zone ranges:
[0.000000] DMA [x0000000000000000 mem 0-0 x000000001fffffff]
[0.000000] Normal empty
[0.000000] Movable zone start for each node
[0.000000] Early memory node ranges
[0.000000] node 0: [x0000000000000000 mem 0-0 x000000001fffffff]
[0.000000] Initmem setup node 0 [x0000000000000000 mem 0-0 x000000001fffffff]
[0.000000] On the node 0 totalpages: 131072
nullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnull