SDRAM from development to the present has experienced five generations, respectively is: the first generation of the SDR SDRAM, the second generation of DDR SDRAM, the third generation of DDR2 SDRAM, the fourth generation of DDR3 SDRAM, the fifth generation of DDR4 SDRAM, with one end of the first generation of SDRAM (Single - Ended) the clock signal, the second generation, the third generation and the fourth generation due to the working frequency is faster, so use can reduce the difference of interfering with the clock signal as a synchronous clock, the SDR SDRAM clock frequency is the frequency of data storage, data reading and writing rate to 100 or 133 MHZ,

Memory chips want to work, you must contact with memory controller, at the same time for a electrical components, power supply is indispensable, and data transmission to a clock as a trigger reference, so the SDRAM when packaging will be set aside for use, the corresponding pin power and clock pin don't need to say more, you can imagine there should be the control pin?

From memory addressing steps down as basic understand, can understand the general situation of the working memory, to note here is that the SDRAM has its own standards for the design of the industry, in the capacity of a standard, standard SDRAM pin/signal can not only consider the design of a bit, but rather to consider a variety of bits wide, and then try to give a general standard, small bits wide chip guild take some pins, the chip may be all but high wide use, but the capacity is not at the same time, the design standards will be different, generally the smaller the capacity of the chips needed pin is also less,

(1) first of all, we know that want to make sure of a memory controller chip, and then to addressing the chip operation, thus to have a piece of signal, it is used to choose chip, the chip will be selected to receive or read the data, so to have a piece of selected signals,

(2) next to the chosen chip of the same of L - Bank address, the number of L - Bank in SDRAM is up to 4, so to have two L - Bank address signal,

(3) the last is the selected chips in the same row/column addressing, address line number to according to the organizational structure of the chip design respectively, but under the same capacity, the number of lines is constant, only the number of columns will be based on a wide and change, the bigger the bits wide and the number of columns is less, because the required storage units have been reduced,

Found after storage unit (4), the chosen chip will undertake unity of data transmission, so must be the same as the a wide number of data I/O channels, so must have the corresponding number of cable pin,