Error (10500) : VHDL syntax Error at the main. VHD (30) near the text "process". Expecting "if"
Code:
The library ieee.
Use the ieee. Std_logic_1164. All;
Use the ieee. Std_logic_unsigned. All;
The entity main is
The port (RST, en: in std_logic;
D_in: in std_logic_vector (2 downto 0);
Din: in std_logic_vector (3 downto 0);
Led0, led1, led2, led3, led4, led5: buffer std_logic_vector (3 downto 0);
Suc: out std_logic;
Nsuc: out std_logic);
End the main;
Architecture behav of main is
The begin
The process (d_in)
The begin
If RST='1' then
Led0 & lt;="0000"; Led1 & lt;="0000"; Led2 & lt;="0000"; Led3 & lt;="0000"; Led4 & lt;="0000"; Led5 & lt;="0000"; Suc<='0'. Nsuc<='0'.
Elsif en='1' then
If d_in="000" then led0 & lt;=din; end if;
If d_in="001" then led1 & lt;=din; end if;
If d_in="010" then led2 & lt;=din; end if;
If d_in="011" then led3 & lt;=din; end if;
If d_in="100" then led4 & lt;=din; end if;
If d_in="101" then led5 & lt;=din; end if;
If d_in="110" then
If (led0 & amp; Led1 & amp; Led2 & amp; Led3 & amp; Led4 & amp; Then suc< led5="001000010100010001100110");='1'. Nsuc<='0'. T<="00"; The else suc<='0'. Nsuc<='1'.
end if;
end if;
end process;
End behav.

CodePudding user response:

A less endif? .

CodePudding user response:

One less end if;

CodePudding user response:

Less a endif, a total of nine if corresponding should have 9 endif only eight in the code

CodePudding user response:

Brother, this is how to return a responsibility?