Create a window shows the following information:
Info: jiema: MegaCore initialization. This may take what you can...
Info: jiema: Variation name: jiema
Info: jiema: Variation language: Verilog HDL
Info: jiema: the Output directory: D: \ 1 tranceiver FPGAsoftware \ practices \ \ rx
Info: jiema: Generating HDL...
Info: jiema: Generating OCP and the constraint files...
Info: jiema: Generating demo testbench files...
Info: jiema: Generating HDL for core...
Info: jiema: Generating MegaCore function of top - level...
Error: jiema: IP Symbol Project Creation Failed. The following Error was returned: & lt; Br> Always run the program "d:/fpgasoftware/quartus12.1/an/altera/" (in the directory" d: \ 1 tranceiver fpgasoftware \ practices \ \ rx \ iptb_8b10b_encoder_decoder_temp2679488714587444728 \ symbol ") : CreateProcess error=5,????? Who?
Error: jiema: Generation failed.

CodePudding user response:

Try directory shorter

CodePudding user response:

Directly created in D set or not, but my directory to only 1 tranceiver \ rx, behind the will automatically add a string, no matter where created