Excuse me: in digital integrated circuit design, how to use Verilog code can be integrated with a fixed delay time delay unit?? I want to input data, for example, after a delay chain late 4 ns output data, wants to use verilog code can be integrated program should be how to write?? Or you can call the FPGA resources to achieve this kind of situation? (# 4 ns this way cannot comprehensive ah ~)

CodePudding user response:

https://wenku.baidu.com/view/6df6888fff00bed5b9f31dc7.html

CodePudding user response:

Begin with # delay cannot be integrated into a hardware circuit delay, comprehensive tools will ignore all delay code, but not an error,

Such as: a=# 10 b;

When the # 10 here is used for simulation of time delay, at the time of comprehensive integrated tool will ignore it, that is to say, on the comprehensive type is equivalent to a=b; ,

What I know is like this

CodePudding user response:

# 4 ns simulation incentive to use, just write tools are not comprehensive,

In the practical use should not less than 4 ns can only say that when I was a delay of output,

At about 1. Constrained by a
2. Then test the actual delay
3. Through manual wiring adjust delay