Verilog design experience a little
1, sensitive variables describe completeness
Verilog, always piece of combinational logic circuit design, expression in the assignment of the right to participate in the assignment all signals must be listed in always @ (sensitive level list), always the if statement in the judgment of the expression must be listed in the sensitive level list, if the assignment expression right refers to the sensitive level not listed in the list of signals, will not listed as a signal when integrated implicitly create a transparent latch, this is because the change of the signal is not immediately caused by the change of the assignment, but must wait until the sensitive level list one signal changes, its effect on performance, which is equivalent to have a transparent latch, the signal changes in the temporary rise, stay sensitive level in the list of a signal change again, pure combinational logic circuit can't do this, comprehensive device will be issued a warning,
Example1:
Input a, b, c;
Reg e, d;
Always @ (a or b or c)
The begin
E=d& A& b;/* d not in the list of sensitive level, d e not immediately when changes, until a, b, c */a certain changes in
D=e | c;
End
Example2:
Input a, b, c;
Reg e, d;
Always @ (a or b or c or d)
The begin
E=d& A& b;/* d in sensitive level list, d e immediately changes */
D=e | c;
End

CodePudding user response:

After waiting for sensitive trigger level list again to read reg d to operation, idea is after this but I don't know the internal integrated why not the same

CodePudding user response:

Learn the,,,,,,,,,,,,,,,,,,

CodePudding user response:

Learning,,,,,,,,,

CodePudding user response:

Still had better write always *