For each bit in a 32 - bit vector, the capture the when the input signal changes in one clock cycle from 1 to 0 on the. The "capture" means that the output will remain 1 until the register is reset (synchronous reset).
Each output bit behaves like a SR flip - flop: The output bit should be set to 1) The cycle after a 1 to 0 The transition occurs. The output bit should be reset to zero) at The positive clock edge when reset is high. If both of The above events occur at The same time, The reset has precedence. In The last 4 cycles of The example waveform below, The 'reset' event occurs one cycle earlier than The 'set' event, so there is no conflict here.
In the example waveform below, reset, In [1] and out [1] are to again separately for clarity.
Here is the answer I wrote
module top_module (
The input CLK,
Input the reset,
In input [31:0],
The output reg [31:0] out
);
Reg [31:0] in_reg;
Always @ (posedge CLK)
If (reset) out & lt; B0=32 ';
The else
The begin
For (int I=0; i<32. + + I)
The begin
If ((in_reg [I]==1) & amp; & (in==0))
The out [I] <=1;
End
End
Always @ (posedge CLK)
The begin
In_reg & lt;=in;
End
Endmodule
The simulation results of the simulation results: YOURS says I, REF simulation results is a standard answer, Mismatch is matching results, the front is matching, near to the 360th CLK me why is not the result of the
CodePudding user response:
If ((in_reg [I]==1) & amp; & (in==0)) if the [I] in it