Be badly in need of help in urgent need of help, this several days to get my head all big,
A parallel ADC circuit recently doing, model is AD9225, 12 bit parallel, range can transform,
I'll use the simplest pin connection, single-ended input 0 to 4 v, in front of a follower,
But how all not line, the output waveform is garbage, garbage to there are fifty noise points, one hundred points very anxious and deviation is large,
The main point is that the voltage at the time of 1 v or so the following may not be able to attend, output is 800, then at the time of more than about 3 v output and full,
1 v to 3 v middle also difficult, the output value is always smaller than the input, the input 2 v in theory should be output 2048, but is probably output about 1800170 0,
Don't know exactly what went wrong, too slowly, the clock in the wire between the capacitive morally also won't have such a big deviation, is really don't understand,
Here is my circuit principle diagram, the upper left corner is the input

CodePudding user response:

Today cut output waveform diagram, 3 v input, it should be morally 3060 m digital waveform output, but the actual waveform is such,
Don't know where the noise, and why the value of output deviation,

CodePudding user response:

Your vref answered the voltage is not correct, try to a voltage source

CodePudding user response:

refer to the second floor fog oasis response:

your vref answered the voltage is not correct, try to a voltage source

Measured voltage is 2 v vref, use an oscilloscope to see once is also very smooth, the problem should not here

Solved the problem yesterday, but did not understand why this is so,

The problem on the clock, if take the oscilloscope probe on the CLK, the result is very accurate and good-looking,
I wonder whether capacitance on the circuit is a little impact on the oscilloscope?

CodePudding user response:

reference Coumen reply: 3/f

Quote: refer to the second floor fog oasis response:

You picked up at the wrong voltage vref, try to a voltage source

Measured voltage is 2 v vref, use an oscilloscope to see once is also very smooth, the problem should not here

Solved the problem yesterday, but did not understand why this is so,

The problem on the clock, if take the oscilloscope probe on the CLK, the result is very accurate and good-looking,
I wonder if a little impact on circuit of capacitance on the oscilloscope,

The dc component in?