//addr=4 eight high humidity
//addr=3 low humidity eight
//addr=2 high temperature 8
//addr=1 low temperature 8
//addr=0 check and eight (after read the address transformation start temperature and humidity)

The module DHT22 (sys_clk, IO_port nReset, replication, nOE, addr, busy, data);

Input sys_clk;//the system clock 1 MHZ
Input replication, nOE, nReset;//chip select | | chip reset data read
Addr input [2-0];//data height 8 bits select
Inout IO_port;
/data/DHT pinThe output data [away];//8 bits of data bidirectional bus
The output busy;//is being read

Wire CHIP_RST;
Tri1 IO_port;
//date interface filtering variable
Reg F_OUT;//filter after the IO - CLK
//chip reset
Reg RST.
//reset DHT22 data
Reg R_FIN;//reset complete
Reg IO_OUT;//reset port
//to read DHT22 data
Reg read_enable;//to read DHT22 data
//a read keep
Reg Read_Begin;
//data bit count
Reg [beat] read_clk_count;//IO read clock counter (sequence)
Reg in_rdy;//read complete
//read clock generation
Reg read_pulse;//a read pulse
//read DHT22 data interface timing process
Reg [39:0] in_buff;//read the data buffer
//pick data
Reg [away] select_bit;


Initial//initializes the internal registers on electricity
The begin
In_rdy & lt;=0;
RST & lt;=0;
Read_pulse & lt;=0;
Read_Begin & lt;=0;
R_FIN & lt;=0;
IO_OUT & lt;=0;
End

The assign data=https://bbs.csdn.net/topics/(! NOE &&! Replication)? Select_bit: 8 'bz.//three states 8-bit data bus, external PS2 data read
The assign IO_port=(IO_OUT)? 1 'b0:1' bz.
The assign busy=read_enable;
The assign CHIP_RST=~ nReset | RST;

//pick data
Always
The begin: select
Case (addr)/* short full_case */
3 'd0:
The begin
Select_bit [away]=in_buff [away].
End
3 'd1:
The begin
Select_bit [away]=in_buff [or];
End
3 'd2:
The begin
Select_bit [away]=in_buff [take];
End
3 'd3:
The begin
Select_bit [away]=in_buff [came];
End
3 'd4:
The begin
Select_bit [away]=in_buff [39:32];
End
Endcase
End

//IO interface filtering
Always @ (posedge sys_clk or negedge nReset)
The Filter
Reg [1:0] IOdat_s;//sampling counter

if (! NReset) begin
IOdat_s & lt;=2 'b0;
F_OUT & lt;=1 'b1;
End
The else begin
If (F_OUT!=IO_port) begin//test data clock jump
If (IOdat_s==2 'd3) begin//3 times sampling ps_clk
F_OUT & lt;=IO_port;
IOdat_s & lt;=0;
End
The else begin
IOdat_s=IOdat_s + 2 'b1;
End
End
The else begin
IOdat_s & lt;=0;
End
End
End

//chip reset
Always @ (nOE)
The begin: C_RST
If (==3 '(addr d0) & amp; & ! Replication & amp; & ! NOE) begin
RST & lt;=1;
End
The else begin
RST & lt;=0;
End
End

//to read DHT22 data
Always @ (negedge nReset or negedge nOE or posedge in_rdy)
The begin: read_first
If (in_rdy | |! NReset) begin
Read_enable & lt;=1 'b0;
End
The else begin
If (==3 '(addr d0) & amp; & ! Replication & amp; & ! The begin in_rdy)
Read_enable & lt;=1 'b1;
End
End
End

//reset DHT22 time-series data process
Always @ (posedge sys_clk or posedge CHIP_RST or negedge read_enable)
The begin: ResetPort
Reg [8-0] R_TIM;//reset time

If (CHIP_RST | |! The begin read_enable)
R_TIM & lt;=0;
R_FIN & lt;=0;
IO_OUT & lt;=0;
End
The else begin
if (! The begin R_FIN)
R_TIM & lt; D1=R_TIM + 9 ';

If (R_TIM==9 'd510) begin
R_FIN & lt;=1;
IO_OUT & lt;=0;
End
The else begin
IO_OUT & lt;=1;
End
End
End
End

//a read keep
Always @ (posedge F_OUT or posedge read_pulse or posedge CHIP_RST)
The begin: Read_keep
If (read_pulse | | CHIP_RST) begin
Read_Begin & lt;=0;
End
The else begin
If (read_clk_count & gt; 1 & amp; & Read_clk_count & lt; 42) begin
Read_Begin & lt;=1;
End
The else Read_Begin & lt;=0;
End
End


//read clock generation
Always @ (posedge sys_clk)
The begin: Read_clk
Reg [beat] sc;

Read_pulse & lt;=0;
If (CHIP_RST) sc & lt;=0;
Else if (Read_Begin & amp; & The begin read_enable)
If (sc<6 'old d40) sc & lt;=sc + 6 'b1;
The else read_pulse & lt;=1;
End
The else begin
Sc & lt;=0;
End
End

//data bit count
Always @ (posedge F_OUT or negedge read_enable or posedge CHIP_RST)
The begin: bit_count
if (! Read_enable | | CHIP_RST) begin
Read_clk_count & lt;=0;
In_rdy & lt;=0;
End
The else begin
Read_clk_count & lt; D1=read_clk_count + 6 ';
If (read_clk_count & gt; 6 'd41) in_rdy & lt;=1;
End
End

//read DHT22 data interface timing process
Always @ (posedge read_pulse or negedge nReset)
The begin: ReadIOData
if (! NReset) in_buff=0;
The else begin
In_buff [moreover] <=in_buff [38:0];
In_buff [0] <=F_OUT;
End
End

Endmodule