` timescale ns/1 ns
The module half_clk_top;
Reg clk_in;
Reg RST.

Initial
The begin
Clk_in=1;
RST=1; # 1000
RST=0; # 1000
RST=1;
End

An affiliate # 200 clk_in=~ clk_in;

Half_clk_dai dai1 (
. Clk_in (clk_in),
RST (RST),
. Clk_out (clk_out)
);
Endmodule