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[the Fpga] Zynq7020 uart using PS side

Time:12-01

I use ALINX black gold ZYNQ7000 AX7020 development board, debug the ps side uart1 (hardware serial port signals received MIO48 and MIO49), in vivado side only need to add the ZYNQ nucleus, and in the peripheral I/O Pins click uart1 48 of the 49 uart1 become green, the other what the default baud rate, and then a lot of work are doing in the SDK, the following code is the inside of the SDK, provide to you, only for reference, but I do to send and receive debug ok, function is normal,

# include & lt; Stdio. H>
# include "platform. H"
# include "xadcps h
"# include "xil types. H"
# include "Xscugic h
"# include "Xil_exception. H"
# include "xuartps. H"
# include "xuartps_hw. H"
# define INTC_DEVICE_ID
KPAR_SCUGIC_SINGLE_DEVICE_ID
# define UART1_IRQ_ID (82)
The static XScuGic ScuGic://GIC
The static XUartPs UartPs
The static void uartFuc ()

CodePudding user response:

Could you tell me if uart0 how should change

CodePudding user response:

Could you tell me how to change if uart0 should
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