The FPGA design block ram, read data exist 100 ps delay, how to explain-CodePudding

Choose in Xilinx FPGA development of block ram (see pg058) as ram read and write operations,
100 ps delay exist in the process of reading data, as shown in figure

Regarding the delay, in pg058 57, relevant time-series show, but there is no delay making detailed explanation of the 100 ps

Everyone a great god, and have to have understanding of the 100 ps delay? Please comment, thank you!!!!!

CodePudding user response:

Expected time is how much or how much time is reasonable, look at the percentage deviation

CodePudding user response:

reference 1st floor dceacho response:

expected time is how much or how much time is reasonable, look at the percentage deviation

Hello, I use the xilinx own block ram IP exsample code simulation is also 100 ps, my question is to design the IP output 100 ps why need? 100 ps this time is determined by what?
See from the datasheet, indeed there is a latch design, and 100 ps is caused by latch, but I don't understand why need to design the latch,

CodePudding user response:

refer to the second floor, please call me Mr Chicken dishes response:

Quote: refer to 1st floor dceacho response:

Expected time is how much or how much time is reasonable, look at the percentage deviation

Hello, I use the xilinx own block ram IP exsample code simulation is also 100 ps, my question is to design the IP output 100 ps why need? 100 ps this time is determined by what?
See from the datasheet, indeed there is a latch design, and 100 ps is caused by latch, but I don't understand why need to design the latch,

The physical nature of the right, I didn't do it the FPGA, but the response time of exposure to various transistor are limited, most of the ns level,
Is your estimate of 100 ps considering the physical reaction time

CodePudding user response:

reference dceacho reply: 3/f

Quote: refer to the second floor, please call me Mr Chicken dishes response:

Quote: refer to 1st floor dceacho response:

Expected time is how much or how much time is reasonable, look at the percentage deviation

Hello, I use the xilinx own block ram IP exsample code simulation is also 100 ps, my question is to design the IP output 100 ps why need? 100 ps this time is determined by what?
See from the datasheet, indeed there is a latch design, and 100 ps is caused by latch, but I don't understand why need to design the latch,

The physical nature of the right, I didn't do it the FPGA, but the response time of exposure to various transistor are limited, most of the ns level,
Is your estimate of 100 ps considering the physical response time

Do you have some truth to this argument, but should not transistors in FPGA, and is sensitive to time, there can be no 100 ps this physical delay exists
Does exist in the design diagram of IP datasheet latch, just don't know the reason why the latch design,

CodePudding user response:

Hello, this problem can you solve it, I met this problem, in the process of simulation is to find a lot of materials also didn't find useful explanation, could you please explain this to me

CodePudding user response:

f _ on the safety reference flowers ___, please reply:

hello, this problem can you solve it, I met this problem, in the process of simulation is to find a lot of materials also didn't find useful explanation, could you please explain this to me?

Finally through some data, indeed there is no clear answer,
In actual use FPGA block memory IP, read latency is 1 cycle,
Function has no effect,,
Ha ha ha ha, I'm sorry, can't give you the correct explanation,

CodePudding user response:

Have a look at The memory/RAM DDR/LPDDR standard spec, there's a bit thin, such as "The read latency (RL) is defined from The last rising edge of The clock that of a read command (Ex: The second rising edge of The CAS - 2 command) to The rising edge of The clock from which The tDQSCK delay is measured. T",