Verilog language, assign a continuous assignment statements, see the following diagram is obtained-CodePudding

CodePudding user response:

Suggestions in this book, regular will write "program"

CodePudding user response:

The

refer to the original poster qq_41391431 response:

Write wrong, don't write "program", and the code has a big problem

CodePudding user response:

Code that's right, can allow such use, simulation, can be integrated,
Choice, this is actually a tristate bus't pick the bus is high resistance and other logic to judge the choice, as long as you can control the ALU, SUM_ALL, LOG, the value of the CALL to avoid selected was no problem at the same time,
Actually reading learning at the same time, some real simulation are helpful to learn more,

 wire [15:0] res; 
Wire [15:0]=16 'log haaaa; 
Wire [15:0] sum=16 'h5555; 
Wire [15:0]=16 'PC h00ff; 

Wire ALU. 
Wire SUM_ALL; 
Wire LOG; 
Wire CALL; 

Reg [3-0] res_cnt_r; 

The assign res=(ALU& SUM_ALL)? Sum: 16 'bz. 
The assign res=(ALU& The LOG)? Log: 16 'bz. 
The assign res=CALL? PC: 16 'bz. 

The assign ALU=res_cnt_r [0]; 
The assign SUM_ALL=res_cnt_r [1]. 
Assign the LOG=res_cnt_r [2]; 
Assign the CALL=res_cnt_r [3]. 

Always @ (posedge CLK) 
The begin 
If (rst_n==0) 
Res_cnt_r & lt;=0; 
The else 
Res_cnt_r & lt;=res_cnt_r + 1; 
End

Look at the results of simulation

CodePudding user response:

reference qq_708907433 reply: 3/f

code that's right, allow this to use, can simulation, can be integrated,
Choice, this is actually a tristate bus't pick the bus is high resistance and other logic to judge the choice, as long as you can control the ALU, SUM_ALL, LOG, the value of the CALL to avoid selected was no problem at the same time,
Actually reading learning at the same time, some real simulation are helpful to learn more,
 wire [15:0] res; 
Wire [15:0]=16 'log haaaa; 
Wire [15:0] sum=16 'h5555; 
Wire [15:0]=16 'PC h00ff; 

Wire ALU. 
Wire SUM_ALL; 
Wire LOG; 
Wire CALL; 

Reg [3-0] res_cnt_r; 

The assign res=(ALU& SUM_ALL)? Sum: 16 'bz. 
The assign res=(ALU& The LOG)? Log: 16 'bz. 
The assign res=CALL? PC: 16 'bz. 

The assign ALU=res_cnt_r [0]; 
The assign SUM_ALL=res_cnt_r [1]. 
Assign the LOG=res_cnt_r [2]; 
Assign the CALL=res_cnt_r [3]. 

Always @ (posedge CLK) 
The begin 
If (rst_n==0) 
Res_cnt_r & lt;=0; 
The else 
Res_cnt_r & lt;=res_cnt_r + 1; 
End 
Look at the results of simulation

Thank you, my own practice under a try,

CodePudding user response:

Code not wrong, it can be used; Upstairs said right, avoid the assign three statements occupy interface is done at the same time,
But suggest design time don't write, best on a assign inside;
Verilog software test, this kind of writing is complains,

CodePudding user response:

Suggestions to find some classic books of digital design, combined with Verilog logic circuit,