Using Verilog HDL design a leap year calculator, calculating the time range is 1900-2100, the year o-CodePudding

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Using Verilog HDL design a leap year calculator, calculating the time range is 1900-2100, the year o

Time：12-01

The 2002 judgment errors, bosses give directions where I wrong? Don't know where there is a problem

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A, b, c, and d are four binary number, the corresponding 16 switch with BAD code said said 0010 0000 0000 0010 2002

CodePudding user response:

Trans module is a bit redundant, but also design the wrong; Actually directly using the input of a, b, c, d, trans output should be 4 - bit, single bit cannot be 0 ~ 9,

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