So-called 18 * 18 multiplier, the multiplier and multiplicand input width up to 18 multiplier, the multiplier to implement circuit is relatively complex, if use the generic logic circuits to build, although also can realize the corresponding function, but the performance is limited by the larger, unable to run at higher clock frequency, thus lower the overall design of the sequential performance, at the same time, using general logic structures, multiplier, will consume more chip area, is not conducive to reduce the cost and power consumption, therefore, in the Cyclone IV E integrated with a certain amount of hardware multiplier, the number of FPGA specific models, ranging from 15 to 266, the hardware multiplier are 18 by default input bits wide, the so-called hardware multiplier, is the multiplier circuit used the hard line logic design, function in chip layout design and layout have been fixed, even if they don't use, the multiplier circuit is also exist, each of the 18 hardware multiplier can be split into two of the nine hardware multiplier is used, or you can use multiple hardware multiplier cascade achieve higher bits wide multiplication, when we need to use the FPGA for high-speed multiplication, using the embedded hardware multiplier is more economic and efficient option,