Me a parallel ADC, 40 Mhz operating frequency, data output rate of 2.5 Mhz, every 2.5 Mhz, ADC produces a pulse signal data effectively, to wait for a period of time just have data, the frequency of the ADC is 100 Mhz, fpga, speaking, reading and writing now to do the ADC result through 100 Mhz FIFO FFT, FIFO write end do you want to generate a 2.5 Mhz clock, can be written in 100 Mhz as a clock, a data for every 40 cycles?
(ADC AD7760)

CodePudding user response:

With asynchronous FIFO FIFO write clock with ADC 40 MHZ, according to the AD7760 read write can make sequential control FIFO, read the FIFO with 100 MHZ,
AD7760 for CPU, use on the FPGA, speaking, reading and writing more troublesome,