cpu-architecture-CodePudding

Tags > cpu-architecture

09-15BlockchainDo I need to use smp_mb() after binding the CPU
09-13databaseEnergy consumption per x86 instruction?
09-05MobileUnderstanding jump address calculation for different bit ISA
08-29Back-endHow to implement a GDB function depending on the architecture
08-28Software designUsing One's Complement In Place of Directly Subtracting Two Binary Numbers
08-17BlockchainHow debuggers deal with out-of-order execution and branch prediction
08-15BlockchainWhy can't we have a safe ISA?
08-12OSWhy is the size of L1 cache smaller than that of the L2 cache in most of the processors?
08-12OSGlobally Invisible load instructions
08-12OSHow to make sure C multithreading program read the latest value from main memory?
08-12OSMSI: When shared and invalid states can occur at the same time
08-06EnterpriseIn a RISC/MIPS-32bit architecture, how does an instruction target a remote memory address that falls
07-29otherWhy are far pointers slow?
07-26MobileInstructions with Long (32 and 64 bit) immediate operands in RISC processors
07-26Software engineeringIs uops.info wrong about vinserti128?
07-25Software engineeringHow caches are connected to cores?
07-24BlockchainHow RISC reducing cycles while having many instructions?
07-23databaseFind minimum and maximum in MIPS
07-19NetCan all of L2/L3 cache be used by data? If so, why does the Graviton 3 bandwidth plot drop off after
07-02Software engineeringHow does bouncing variables between two local L1 caches makes the code slower?
06-27databasec 11: how to produce "spurious failures" upon compare_exchange_weak?
06-11front endWhy does MOVD/MOVQ between GP and SIMD registers have quite high latency?
06-02NetDoes RSQRTSS break the dependency on the destination register?
05-30Software designIs a schedulable unit of CPU time slice process or thread?
05-26BlockchainWhat's differences between address space, addressability, word-addressable, addressing mode?
05-24BlockchainRISCV branchless coding
05-24BlockchainUnderstanding address assignment to registers via assembly instructions
05-23Blockchaingdb-multiarch (MINGW64) cannot determine architecture from executable?
05-20Back-endSpeed miracles in x86/amd64 land: evaluating a polynomial for every i in a loop gets slower with f
05-12NetWhy didn't x86 implement direct core-to-core messaging assembly/cpu instructions?
05-02MobilePerformance differ significantly when inner loop iterates less times?
04-28NetAssuming that you had a MIPS processer with PIPELINE but without hazard prevention nor forwarding, w
04-22NetWhy does this piece of code written using uint8_t run faster than analogous code written with uint32
04-15Software engineering8086 lock pin and ASM LOCK prefix how it works
04-07MobileWhy is the Overflow-Flag only set when single shifts are used?
04-04EnterpriseWhat happens to outstanding stores after an object is deleted?
03-15Back-end5-Stage RISC - How are loads handled?
03-08databaseRun time and reported cycle counts in linux perf
03-04NetHow can I perform a hex memory dump on an address in memory?
03-01otherAre IA-32 segment descriptors that do not cover the full 4GiB linear address space slower?

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